• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The present invention provides a method of manufacturing a multi-layered wiring structure of a semiconductor device in which the thickness of the photoresist film is reduced to improve the resolution of pattern formation, and a highly reliable semiconductor device can be manufactured using an improved via hole mask. In order to achieve the object of the present invention, the first insulating layer 32, the first etching termination layer 33, the second insulating layer 34, and the second etching termination layer 35 are sequentially formed on the lower conductive layer pattern 31. The second etching finish layer 35, the second insulating layer 34, and the first etching finish layer 33 are etched to form a trench 37 having a shape corresponding to the upper conductive layer pattern. A photoresist film is formed on the entire surface of the upper surface of the semiconductor substrate so that a thin photoresist film having a thickness of about 1000 to 3000 micrometers is formed on the second etch finish film 35, and then photolithography is performed on a predetermined portion of the trench 37. An opening 38 is formed, the first insulating layer 32 is etched through the opening 38 to form a via hole 40, and a conductive material is formed in the via hole 40 and the trench 37. Provided is a method of manufacturing a multilayer wiring structure of a semiconductor device including a filling step.
    公开号:KR19990087024A
    申请号:KR1019980060251
    申请日:1998-12-29
    公开日:1999-12-15
    发明作者:윤진영；김영철
    申请人:김영환；현대반도체 주식회사；
    IPC主号:
    专利说明:

    Method for manufacturing multilayer wiring structure of semiconductor device
    BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer wiring structure of a semiconductor device, and more particularly, to a method for manufacturing a multilayer wiring structure of a semiconductor device using a dual damasence process.
    As the degree of integration of semiconductor elements has increased, it has become common to adopt a three-layer wiring or a multilayer wiring structure of more. Conventionally, in order to manufacture such a multi-layered wiring structure, a lower conductive layer pattern is formed on a semiconductor substrate, and an insulating layer is formed on the lower conductive layer pattern to electrically insulate the upper conductive layer pattern from the lower conductive layer pattern. Selectively etching the insulating layer to form a via hole for connecting the lower conductive layer pattern to the upper conductive layer pattern, forming a conductive layer on the via hole and the insulating layer pattern, and then patterning the upper conductive layer pattern It was possible to achieve by repeating the step of forming a. However, according to the conventional manufacturing method of the multilayer wiring structure, there is no big problem in the production of the multilayer wiring of about one layer or two layers, but in the three-layer or more multilayer wiring structure, the higher the number of wiring layers is on the semiconductor substrate Problems such as shortening between the upper and lower conductive layer patterns and disconnection of the conductive layer pattern occurred due to the increased level of the formed structures.
    In order to solve such a problem, the manufacturing method of the multilayer wiring structure called the damascene method was started. That is, an insulating layer is formed on the lower conductive layer pattern, and the insulating layer is etched to form a via hole in a position corresponding to a trench corresponding to the upper conductive layer pattern and an interconnection connecting the upper conductive layer and the lower conductive layer. In this case, the trench and the via hole are filled with a conductive film. According to this method, since the uppermost conductive layer pattern is formed even after the upper conductive layer pattern is formed, the short circuit and the wiring between the wirings are disconnected even when the multilayer wiring process is performed. There is no problem and the reliability of the semiconductor device is improved.
    A method for manufacturing a multilayer wiring structure according to the conventional inlay method is described in detail in US Pat. No. 4,789,648. An example of a method of manufacturing a multilayer wiring structure of a semiconductor device using a conventional damascene method is as follows.
    First, as shown in FIG. 1A, a lower conductive layer pattern 12 is formed on a semiconductor substrate 11, and a first oxide film as an insulating film is formed on the lower conductive layer pattern 12 and the upper surface of the semiconductor substrate 11. (13) is formed. Next, a nitride film is formed as an etch stop film 14 on the oxide film 13, and a second oxide film 15 is formed as an insulating film on the etch finish film 14. The etch stop layer is formed to a thickness of about 1500 kPa and the second oxide film is formed to a thickness of about 5000 kPa.
    Next, as shown in FIG. 1B, the second oxide film 15 is partially etched to form a trench 16 having a shape corresponding to the upper conductive layer pattern. The total depth of the trench 16 is about 6500 mm by adding the thickness of 1500 mm of the etch finish film to 5000 mm of the second oxide film.
    Next, a photoresist film is formed over the entire structure of FIG. 1B. At this time, the thickness of the photoresist pattern on the second oxide film 15 is about 8000 to 10,000 Å. If the thickness of the photoresist film on the second oxide film 15 becomes thinner than 8000 kPa, the photoresist film may be etched and etched down to the second oxide film 15 under the etching process for forming the via hole. Therefore, in order to prevent the etching of the second oxide film 15, the thickness of the photoresist film on the second oxide film 15 is sufficiently thick. In addition, in order to form a thickness of the photoresist film pattern on the second oxide film 15 to a thickness of about 8000 to 10,000 Pa, it is formed by rotating coating a photoresist having a viscosity of about 8 cps at 2000 rpm to 3000 rpm. Cp, which is a unit representing the viscosity, is an abbreviation of centi-poise, and is a unit representing the relative viscosity of a solution when the viscosity of water is 1 cp. On the other hand, since the photoresist film has a very low viscosity and is formed by the rotation coating method, the height of the top surface of the photoresist film and the height of the top surface of the photoresist film in the trench are almost the same on the oxide film. Accordingly, the thickness of the photoresist pattern in the trench 11 is about 14500 to 16500 kPa, which is the thickness of the trench plus the thickness of the photoresist film formed on the oxide film.
    Next, as shown in FIG. 1C, to form a via hole, a window 18 is formed by performing a photolithography process on a predetermined portion of the photoresist film on the trench 16. The photoresist film becomes a photoresist film pattern 17 having a window 18. Next, the first oxide layer 13 is etched through the window 18 using the photoresist pattern 17 as a mask, and the photoresist layer pattern 17 is removed to form a via hole 19 as shown in FIG. 1D. do.
    Next, a conductive layer (not shown) is formed on the entire structure of FIG. 1D to fill the via hole 19 and the trench 16, and then a chemical mechanical polishing process is performed to form the upper conductive layer pattern 20 and the upper conductive layer pattern 20 as shown in FIG. 1E. The connection portions 21 connecting the upper and lower conductive layer patterns 12 and 20 are formed at the same time.
    However, in the conventional method of manufacturing a multilayer wiring structure as described above, there is a problem in that photoresist patterning for forming via holes is required in a state in which the thickness of the photoresist film in the trench is 14500 to 16500 kPa. However, in the general photolithography process, the thicker the resist film is, the lower the resolution limit is. That is, as shown in Fig. 7, when the thickness of the photoresist film is 6900Å, the obtained resolution limit pattern width is 0.18um, but when the thickness of the photoresist film is 10400Å and 11800Å, it is 0.22um and 0.26um, respectively. The resolution margin line becomes thicker. That is, when the thickness of the photoresist film is thick, it can be seen that it is difficult to form a fine pattern. In order to manufacture the latest 256M DRAMs and higher-grade DRAMs, the design rule of 0.18 um or less is aimed. Therefore, such a problem is difficult to achieve because the thickness of the photoresist film is thick in the same manner as in the conventional process. There was.
    In addition, in the photolithography process currently being developed, the margin of focus depth is generally about 0.4 to 0.6 µm. In the conventional art, however, since the thickness of the photoresist film is 14000 GPa or more, even when the maximum depth of focus margin is applied, the thickness of the photoresist film is twice as large as the depth of focus margin, that is, 12000 GPa or more. Since the depth margin is out of range, the photoresist film may not be resolved well. In particular, when the via hole has a fine hole of about 0.3 μm or less, there is a problem in that a via hole is not formed due to a bridge phenomenon between photoresist patterns.
    In addition, since a mask having an opening corresponding to the size of the via hole is formed when the via hole mask is conventionally formed to form the via hole in a predetermined portion of the trench, the size of the via hole actually formed when the alignment is not proper. As a result, the size of the via hole is reduced compared to the size of the via hole, and there is a problem such as an increase in contact resistance or a poor contact between the upper and lower layers.
    SUMMARY OF THE INVENTION The present invention has been made in view of the conventional problems, and an object of the present invention is to provide a method for manufacturing a multilayer wiring structure of a semiconductor device for manufacturing a highly reliable semiconductor device by increasing the resolution by thinning a photoresist film.
    The present invention also provides a semiconductor device capable of manufacturing a highly reliable semiconductor device by forming an improved via hole mask having an opening larger than the size of the via hole when the via hole mask is formed, thereby preventing contact failure and increase in contact resistance between upper and lower layer wirings. It provides a method for producing a multilayer wiring structure of.
    In order to achieve the object of the present invention, the first insulating film, the first etching finish film, the second insulating film and the second etching finish film is sequentially deposited on the lower conductive layer pattern, the second etching finish film, the second insulating film, The first etch finish layer is etched to form a trench having a shape corresponding to the upper conductive layer pattern, and a thin photoresist film having a thickness of about 1000 to 3000 mV is deposited on the second etch finish layer so as to form a photoresist on the entire surface of the upper structure of the semiconductor substrate. After forming a resist film, photolithography is performed to form an opening 38 in the predetermined portion of the trench, and to etch the first insulating layer through the opening to form a via hole, and to form a conductive material in the via hole and the trench. Provided is a method of manufacturing a multilayer wiring structure of a semiconductor device including a filling step.
    The opening may be a rectangular, elliptical, or linear shape having a long length in a direction perpendicular to the longitudinal direction of the trench, and at least partially exposing an upper surface of the second etch finish layer. It provides a manufacturing method.
    1A to 1E are process flowcharts showing an example of a method for manufacturing a multilayer wiring structure of a conventional semiconductor device.
    2A to 2F and 3A to 3F are flowcharts of a manufacturing process of a multilayer wiring structure of a semiconductor device according to the present invention.
    4A and 4B show another embodiment of the present invention corresponding to the process of FIGS. 2C and 3C, respectively.
    5A and 5B show another embodiment of the present invention corresponding to the process of FIGS. 2C and 3C, respectively.
    6 is a plan view of the case where the via hole mask is misaligned.
    7 is a graph showing the relationship between the design line width and the actual resolution line width according to various thicknesses of the photoresist film.
    Fig. 8 is a graph showing the relationship between the wafer rotational speed and the thickness of the formed photoresist film upon application of the photoresist film according to the viscosity of the photoresist film.
    ***** Explanation of Drawings *****
    31 lower conductive layer pattern 32 first insulating film
    33: first etching finish film 34: second insulating film
    35 second etching finish layer 36 first photoresist pattern
    37: trench 38, 38a, 38b: opening
    39, 39a, 39b: second photoresist pattern 40: via hole
    41 metal film 41a upper conductive layer pattern
    41b: connection
    A method of manufacturing a multilayer wiring structure according to the present invention will be described with reference to FIGS. 2A to 2F and 3A to 3F. 2A to 2F are plan views showing a process sequence for manufacturing a multilayer wiring structure of the semiconductor device of the present invention, and FIGS. 3A to 3F are line IIIi-IIIi (i = a to f) of FIGS. 2A to 2E, respectively. According to the longitudinal section. Accordingly, the same reference numerals denote the same components when the respective reference numerals of FIGS. 2A to 2F and the reference numerals of FIGS. 3A to 3F mean the same components.
    First, a lower conductive layer pattern 31 is formed on a semiconductor substrate (not shown) as shown in FIG. 2A or 3A (FIG. 3A is a longitudinal cross-sectional view along the line IIIa-IIIa in FIG. 2A). The material of the lower conductive layer pattern is preferably formed of aluminum (Al) or copper (Cu). In addition, a first insulating layer 32 of about 5000 kV is formed on the lower conductive layer pattern 31 and the semiconductor substrate (not shown). Next, on the first insulating film 32, a first etch finish film 33 of about 1500 mW, a second insulating film 34 of about 5000 mW, and a second etch finish film 35 of about 1000 mW are sequentially formed. . The material of the first insulating film 32 and the second insulating film 34 is a silicon oxide film or a TEOS film (tetra-ethyl-orthosilicate) formed by plasma enhanced chemical vapor deposition (PECVD). In this case, the first etch stop layer and the second etch stop layer are preferably silicon nitride films (SixNy) having a high etching selectivity with respect to the silicon oxide film or the TEOS film as the first and second insulating film materials.
    Next, a first photoresist pattern 36 having a thickness of about 5000 mW is formed on the second etch finish layer 35. Since the first photoresist pattern 36 serves as a mask for forming a trench, the first photoresist pattern 36 is referred to as a trench mask.
    Next, as shown in FIG. 2B or 3B (a longitudinal cross-sectional view along the line IIIb-IIIb of FIG. 2B), the second etching finish layer 35, the second insulating layer 34, and the first insulating layer 35 are formed using the trench mask 36. The etching stop layer 33 is sequentially etched to form the trench 37.
    Next, the trench mask 36 is removed. The bottom of the trench 37 is an upper surface of the first insulating layer 32. In addition, the trench 37 has a depth of about 7500 kPa including the thicknesses of the first insulating film and the first and second etching finish films.
    Next, as shown in FIG. 2C or FIG. 3C (a longitudinal cross-sectional view along the IIIc-IIIc line in FIG. 2C), a second photoresist film is formed on the entire structure of FIG. 2B or FIG. 3B, wherein the second etching is performed. The thickness of the second photoresist film on the finish film is about 1000 to 3000 mm 3. In this case, a photoresist film of 8500-10500 kV is formed in the trench in which the depth of the photoresist film formed on the second etch finish film, that is, the thickness of the photoresist film formed on the second etching finish film, i. Next, an open portion 38 for forming a via hole is formed by performing a photolithography process on the second photoresist film. As a result, the second photoresist film becomes a second photoresist film pattern 39 having an opening 38. In addition, since the second photoresist film pattern 39 is a mask for forming a via hole, it is referred to as a via hole mask hereinafter. When the via hole mask is formed, the thickness of the photoresist film in the trench is 8500 to 10500 mm3, which is much thinner than that of the conventional 14500 mm to 16500 mm3, thereby improving the resolution. Such effects can be seen well from the graph of FIG. In other words, the thinner and thinner the photoresist film, the better the resolution. Therefore, there is an effect that can cope with the pattern miniaturization according to the miniaturization of the semiconductor device. In addition, since the depth of focus margin in the general photolithography process is 0.4 to 0.6 µm, when the center of the photoresist film having a thickness of 8500 to 10500 microns is focused, it is sufficiently exposed from the top surface to the bottom surface, and a bridge is formed when forming fine holes. The problem goes away.
    On the other hand, the relatively thin photoresist film as described above can be formed by the following method. That is, in the related art, a photoresist film was coated while rotating a semiconductor substrate at 3000 rpm using a photoresist having a viscosity of about 8 cps to form a photoresist film of about 8000 kPa. However, in order to form a photoresist film of 3000 kPa or less required by the present invention, as shown in FIG. 8, there is a method of maintaining the rotation speed of the semiconductor substrate at 3000 rpm and lowering the viscosity of the photoresist to 2 cps. In addition, as a method of lowering the viscosity of the photoresist, the content of a solvent in the components of the photoresist may be increased. In the case of the photoresist having a viscosity of about 5cp, the solvent content is about 80%. Therefore, it is desirable to lower the viscosity by increasing the content of the solvent (solvent) to about 90-95% to lower the viscosity. In addition to the method of lowering the viscosity of the photoresist as described above, there is a method of maintaining the viscosity of the photoresist as it is and increasing the rotational speed of the semiconductor substrate during coating of the photoresist film. That is, as shown in Fig. 8, in order to make the thickness of the resist 3,000 Pa or less, when using a photoresist having a viscosity of 5 cp, a photoresist film is formed in a state having a rotation speed of about 6000 rpm or more. That is, the thickness of the photoresist film can be controlled by lowering the viscosity or increasing the rotation speed of the semiconductor substrate during the coating of the photoresist film.
    In addition, the opening 38 of the via hole mask 39 of FIG. 2C has a length of the trench 37, as shown in FIG. 4A or 4B (a longitudinal cross-sectional view along the line IIIc'-IIIc 'of FIG. 4A). It is preferable that the rectangular or oval shape 38a having a long length in the direction orthogonal to the direction is larger than the intended size of the via hole. When the opening 38 has an ellipse shape, the diameter of the major axis a of the ellipse is larger than the diameter of the intended via hole, and the direction of the major axis is a direction perpendicular to the longitudinal direction of the trench. In addition, the diameter of the minor axis (b) of the ellipse is equal to the size of the intended via hole.
    In addition, the opening portion 38 may also form a linear opening portion 38b formed in a direction orthogonal to the longitudinal direction of the trench 37, as shown in Figs. 5A and 5B. As shown in FIGS. 4A and 5A, the size of the opening is larger than the size of the intended via hole (the size of the opening 38 of FIG. 2C) in the direction orthogonal to the length direction of the trench. have. That is, when the via hole mask 39 is formed, the alignment of the pattern with the trench 37, which is already formed, must be precisely performed. If the alignment is incorrect, the opening 38 of the via hole mask 39 is left (or shown in FIG. 6). When moved to the right), the area of the trench 37 exposed through the opening 38, that is, the intersection 50 of the trench 37 and the opening 38 (indicated by a dot in the drawing) is reduced. . As a result, in the subsequent via hole etching process, the size of the via hole is smaller than the intended size, resulting in an increase in connection resistance between the upper layer wiring and the lower layer wiring, or a connection failure.
    However, as shown in Figs. 4A and 5A, when the openings 38a and 38b are formed to be larger than the size of the desired via hole, a misalignment error in the left or right direction during exposure for forming the second photoresist pattern 39 is caused. There is an advantage that the size of the via hole does not decrease even if it occurs.
    In the present invention, an important factor that can be formed larger than the size of the via hole intended for the opening for forming the via hole as described above is that the second etching finish film is formed on the second insulating film. That is, even when the size of the opening is oversizing larger than the intended via hole, the second insulating layer is prevented from being etched during the via hole etching process, thereby maintaining the shape of the trench 37. However, the size of the opening in the longitudinal direction of the trench should not be increased. Since the etch stop layer is not formed on the bottom of the trench, when the size of the opening in the trench length direction increases, the first insulating layer is etched to the size of the opening, which is larger than the intended size of the via hole.
    As described above, when the via hole masks 39, 39a, and 39b are formed, the first insulating layer 32 on the bottom surface of the trench 37 is etched using the via hole masks 39a, 39b, and 39c. A via hole 40 having a structure such as 2d is formed. In this case, the etching process is preferably a high density plasma reactive ion etching (HDP RIE) process using a mixed gas of C 2 F 6 gas and C 4 F 8 gas. FIG. 2D is a via hole formed using the second photoresist pattern 39b of FIG. 5A as a mask. The longitudinal cross-sectional view along the IIId-III line of Fig. 2d is the same as that of Fig. 3d. Next, the via hole mask 39b is removed.
    Next, a metal film, which is a conductive material, is deposited on the entire surface of the structure of FIG. 2D. In particular, the metal film was made of aluminum (Al) or copper (Cu). The metal film is deposited to a sufficient thickness so as to completely fill the via hole 40 and the trench 37 and to be formed on the top surface of the second etching finish film 35. As a result, the structure of Fig. 2E is obtained. FIG. 3E is a longitudinal sectional view taken along line IIIe-IIIe of FIG. 2E; Next, a chemical mechanical polishing process is performed on the structure of FIG. 2E until the second insulating film 34 is exposed to complete the manufacture of the multilayer wiring structure of the semiconductor device as shown in FIG. 2F. FIG. 3F is a longitudinal cross-sectional view taken along line IIIf-IIIf in FIG. 2F. As a result, the manufacture of the multilayer structure of the semiconductor device having the upper conductive layer 41a filling the trench 37 and the connecting portion 41b of the upper conductive layer 41a filling the via hole 40 and the lower conductive layer 31 is completed. .
    According to the present invention, a method of manufacturing a multilayer interconnection structure using a double damascene method in which an etch finish film is formed on an uppermost surface of a multilayer insulating film, wherein the etch finish film is formed in a trench after forming a via hole mask to form a via hole. Since the thickness becomes thinner than in the related art, the resolution of the pattern is improved and as a result, the reliability of the semiconductor device is improved. In addition, when forming the via hole mask for forming the via hole, the size of the via hole caused by the alignment error is prevented, thereby solving the problem of contact resistance and poor contact of the wiring, thereby improving the reliability of the semiconductor device.
    权利要求:
    Claims (6)
    [1" claim-type="Currently amended] Sequentially forming a first insulating film, a first etching finish film, a second insulating film, and a second etching finish film on the conductive layer pattern;
    Etching the second etching finish film, the second insulating film, and the first etching finish film to form a trench;
    Forming a photoresist film on an upper surface of the second etching finish film and in the trench;
    Forming an opening in the photoresist film at the predetermined portion of the trench to expose the top surface of the first insulating film;
    Forming a via hole by etching the exposed first insulating layer to expose a portion of the conductive layer pattern;
    And filling a conductive material into the via hole and the trench.
    [2" claim-type="Currently amended] The method of claim 1,
    The opening portion has a long rectangular shape in a direction orthogonal to the longitudinal direction of the trench, at least part of the upper surface of the second etch finish film through the opening portion is a method for manufacturing a multi-layer wiring structure of a semiconductor device.
    [3" claim-type="Currently amended] The method of claim 1,
    The opening is an ellipse, the ellipse is a method of manufacturing a multi-layered wiring structure of a semiconductor device, characterized in that the diameter in the direction perpendicular to the longitudinal direction of the trench is larger than the diameter in the longitudinal direction of the trench.
    [4" claim-type="Currently amended] The method of claim 1, wherein a thickness of the photoresist film on the second etch finish film is about 1000 to about 3000 μs.
    [5" claim-type="Currently amended] The method for manufacturing a multilayer wiring structure according to claim 4, wherein the step of forming the photoresist film is a method of coating a semiconductor substrate while rotating at 3000 rpm or more using a photoresist having a viscosity of 2 cps.
    [6" claim-type="Currently amended] The method of claim 4, wherein the forming of the photoresist film is performed by coating the semiconductor substrate while rotating at 6000 rpm or more using a photoresist having a viscosity of 5 cps.
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    同族专利:
    公开号 | 公开日
    KR100307528B1|2001-11-02|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1998-05-28|Priority to KR1019980019455
    1998-05-28|Priority to KR19980019455
    1998-05-28|Priority to KR98-19455
    1998-12-29|Application filed by 김영환, 현대반도체 주식회사
    1999-05-14|Priority claimed from JP13344299A
    1999-12-15|Publication of KR19990087024A
    2001-11-02|Publication of KR100307528B1
    2001-11-02|Application granted
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019980019455|1998-05-28|
    KR19980019455|1998-05-28|
    KR98-19455|1998-05-28|
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